There are a number of interesting technologies to keep an eye on in term of how and when they could be adopted for use in SoC design today, some of which include gallium arsenide, GPGPUs, 3D ICs and ...
Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore’s Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around ...
Asynchronous processors, which function without a global clock, have emerged as a compelling alternative to traditional synchronous architectures. Their design relies on handshake protocols and local ...
For a useful primer on circuit design, see Optimize your DSPs for power and performance. To learn how power and performance vary with voltage and temperature, see Push performance and power beyond the ...
Grenoble, France – June 07, 2010 – Tiempo,SAS, a developer of innovative clockless technology for the design of low power integrated circuits (ICs), today announced its ability to support the use of ...
Given the growing importance and impact of portable, battery-operated devices in today’s society, it’s easy to understand why power consumption has become such a critical factor in IC design. But it’s ...
“We’re replacing dictatorship with anarchy!” Karl Fant tells me emphatically. Ponytailed and animated, the founder and chief technical officer of Theseus Logic fills the whiteboard with sweeping ...
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