EDN

Agere to pull Cadence partitioning, sign-off tool into ASIC flow

ALLENTOWN, Pa. — Agere Systems is working with San Jose, California-based Cadence Design Systems Inc. to provide Agere ASIC customers with access to Cadence's “First Encounter” EDA software. This is ...
Design And Reuse

Cadence Collaborates with TSMC to Accelerate Design of Next-Generation AI Silicon

Expanding partnership enables Cadence’s Design for AI and AI for Design strategy across TSMC’s N3, N2, A16 and A14 process nodes​. Developing “agent‑ready” digital and ...
EDN

Chip-building tool supports Cadence flow

San Jose, Calif. – ReShape Inc. said its PD Builder chip construction tool now supports the ASIC/system-on-chip design flow of Cadence Design Systems Inc. ReShape introduced PD Builder earlier this ...
Nasdaq

GUC Optimizes Quality of Results and Accelerates Time to Tapeout Using the Cadence Digital Full Flow

Cadence’s Innovus Implementation System mixed-placer automation delivers more than 10% wirelength reduction and 5% better switching power GUC reduces floorplan design time from weeks to days, ...
Design And Reuse

Cadence and NVIDIA Expand Partnership to Reinvent Engineering for the Age of AI and Accelerated Computing

At CadenceLIVE Silicon Valley 2026, Cadence (Nasdaq: CDNS) announced an expanded partnership with NVIDIA to deliver accelerated solutions across agentic AI, physics-based simulation and digital twins ...