EDN

Clock generators achieve low jitter up to 2 GHz

Houston, Tex. — VMETRO Inc. has introduced a high-frequency clock generator PMC/XMC module. The XCLK1 module provides up to five phase matched, low jitter, sample clocks for high-speed ...
EDN

Low-jitter clock generator has DC to 2.05 GHz frequency range

The Stanford Research Systems CG635, available in the UK from TTi (Thurlby Thandar Instruments), is a low-jitter clock generator which can provide a wide range of clean, precise clocks for the most ...
Semiconductor Engineering

All-Digital MDL-Based Fast Lock Clock Generator For Low-Power Chiplet-Based SoC Design

A new technical paper titled “A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems” was published by researchers at Hongik University, Seoul, South Korea. “An all-digital ...
Electronic Design

Timing Decisions 102: Optimize Your Clock Tree

The importance of timing requirements and jitter budgets for FPGAs, ASICs, and SoCs. How to utilize the information portrayed in a clock tree to choose the most well-suited clock generator for your ...
Electronic Design

How BAW Clocks Redefine ADAS and IVI Systems

Members can download this article in PDF format. Just like Goldilocks, the market for advanced driver-assistance systems (ADAS) and in-vehicle infotainment (IVI products) knows when something is just ...