As System-on-Chip (SoC) designs grow ever larger, design and verification flows are changing. A rich mix of features, increased software content, high intellectual property (IP) use and submicron ...
SAN MATEO, Calif. — In conjunction with Tera Systems Inc., LSI Logic Corp. has put together a methodology and tool flow that let customers know up-front if they are developing register-transfer-level ...
The standard approach for testing IC logic is the use of scan chains, with embedded compression as the standard approach for applying scan patterns. Embedded compression enables the same test quality ...
The RTL Architect product represents the industry's first physically aware RTL analysis, optimization, and signoff system built on a fast, multi-dimensional prediction engine for superior RTL handoff ...
High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this ...
Embedded memories are consuming a growing portion of overall die area. Thus, designers of systems-on-a-chip (SoCs) for embedded systems should consider a design flow that guides users through the ...
If you are one of the more than 2 billion smartphone users today, it is hard to imagine life without one! Breaking new frontiers, wearable smart devices and the Internet of things are the latest buzz.
New design languages and new chips and systems mean a whole new set of design gotchas for today's developers. Once-simple tasks become difficult and, thankfully, once-difficult tasks become easy. This ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback