Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore’s Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around ...

Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...

Given the growing importance and impact of portable, battery-operated devices in today’s society, it’s easy to understand why power consumption has become such a critical factor in IC design. But it’s ...

Managing the power consumption of ICs is an increasingly difficult challenge, because each new generation of portable device includes expanded features and demands longer battery lives.

For a useful primer on circuit design, see Optimize your DSPs for power and performance. To learn how power and performance vary with voltage and temperature, see Push performance and power beyond the ...